Today's integrated circuit (IC) industry is driven almost completely by the pursuit of lower cost without sacrificing performance. To achieve this, circuit designers look for ways to reduce the IC die area as they develop attractive solutions to make IC devices more desirable to their customers. In the newly expanding Class-D audio amplification area, an attractive idea is to provide a Class-D amplifier system that runs on a digital pulse width modulation (PWM) input. This is advantageous as it greatly reduces the amount of die area by eliminating the necessity of using a digital-to-analog converter (DAC), thus lowering the cost of production and of implementation.
PWM is obtained by taking a stream of electrical pulses and varying their widths, i.e., their duration in time, as a function of an input. The simplest type of PWM generation is called Natural-PWM (NPWM), and involves comparing the input waveform, which is an analog input, with a triangle wave at a frequency of fc. In addition, the continuing expansion of digital techniques in the field of audio has led to a different type of PWM generation called Uniform-PWM (UPWM) which typically uses a higher order digital modulator to convert a digital Pulse Coded Modulation (PCM) signal to a uniformly sampled PWM. In addition to the sampling method, PWM is traditionally also differentiated by the edge modulation type and by the class. The modulation may also be single sided or double sided. Class AD and Class BD are the standardized abbreviations used to differentiate between two-level and three-level switching.
Once a PWM signal is generated, it can be used to drive a high power output field effect transistor (FET) array. Due to the bi-level nature of a PWM signal, each transistor will be either completely on or completely off, as a result of which the power stage will have a higher efficiency than other analog power stages.
However, even using an ideal NPWM (and UPWM), a subsequent switching power stage will generally add noise and distortion due to switching delays that vary non-linearly with load current. Errors can also be induced by a lower quality triangle wave signal. Similarly, noise and ripple on the power supply for the switching power stage will introduce errors in the system output signal resulting in poor Total Harmonic Distortion (THD) and Power Supply Rejection Ratio (PSRR).
It is known from delta-sigma (Δ-Σ) converter theory that using an integrator before a noise adding element and then feeding back the inverse of the output pushes the added errors high into the frequency band. If the errors are pushed above the audio band, an external low-pass filter can be used to extract the audio signal from the PWM waveform. The same principle has been used for many existing Class-D architectures. Most of the existing architectures for Class-D operate on analog inputs and hence require the presence of a DAC, and also need an analog ramp at the input of the comparator to generate the PWM output.
Although prior art architectures can also work with digital PWM inputs, they still need an analog ramp at the input of the comparator. This is not very desirable since the presence of an analog ramp can create intermodulation distortion because of the carrier modulating with the PWM input. In order to avoid this, the ramp frequency and the carrier frequency of the digital PWM input should be perfectly matched. This is a very tight factor to control.
A prior art solution has been proposed that uses a square wave feeding in into the integrator in order to create a ramp. However, this architecture does not completely eliminate intermodulation distortion due to the square wave modulating with the input PWM's carrier. Solutions that have been proposed to overcome this are generally not area effective, because of the size of the passive devices that end up being required. Furthermore, the presence of clock jitter and duty cycle modulation can also cause noise in the system.
Still further, in a generic, single-ended Class-D amplifier, the common-mode value of the integrator should change based on the voltage of the power supply, e.g. battery. However, prior art techniques for achieving this, while improving the PSRR, do so at the cost of a large amount of silicon area, because, for example, they do so by adding either a very large RC filter on the chip or by using an extra pin to connect to an external RC filter, in both cases to create a sub-Hertz pole.